With the rapid development of electronic industry, electronic products are gradually trending towards multifunction and high performance. Different package types have been developed in the current semiconductor package structures, such as wire-bonding package or flip-chip package. A semiconductor chip is disposed on a packaging substrate, and the semiconductor chip is electrically connected to the packaging substrate by bonding wires or solder bumps. In order to meet the packaging demands for highly integrated and miniaturized semiconductor package devices for connecting more active and passive components and wires, the packaging substrate is gradually evolved into a multi-layer board. Within the limited space of the packaging substrate, interlayer connection technology is available to expand circuit layout areas on the packaging substrate in order to meet the demands for high-density integrated circuits and reducing the thickness of the packaging substrate for achieving a low-profiled and compact-sized package structure, and also improving electrical functions.
In the prior art, a packaging substrate is constructed by a core board having the inner layer circuit and a circuit built-up structure symmetrically formed on both sides of the core board. It results in an increase in the thickness of the entire structure due to the use of the core board. Therefore, it is difficult to meet the demands for improving the functionality of electronic products and shrinking the volume of electronic products.
Accordingly, a coreless packaging substrate is developed for shortening the wire length and reducing the thickness of the entire structure, in order to meet the trend of high frequency and miniaturization. As shown in FIG. 1, a coreless packaging substrate 1 is formed by the following steps of: forming a first dielectric layer 120a on the carrier board (not shown), and forming a first circuit layer 11 on the first dielectric layer 120a; forming a circuit built-up structure 12 that has a second, a third, and a fourth dielectric layers 120b, 120c, 120d on the first dielectric layer 120a and the first circuit layer 11, the circuit built-up structure 12, and forming a second circuit layer 121 on the second to fourth dielectric layers 120b, 120c, 120d, wherein each second circuit layer 121 is electrically interconnected by conductive vias 122; removing the carrier board for exposing the first dielectric layer 120a; forming a masking solder resist layer 14a, 14b on the first dielectric layer 120a, the fourth dielectric layer 120d, and the second circuit layer 121, respectively; forming an opening 140a in the solder resist layer 14a and the first dielectric layer 120a for exposing a portion of surface of the first circuit layer 11, and forming an opening 140b in the solder resist layer 14b for exposing a portion of surface of the second circuit layer 121; forming metal bumps 13a, 13b in the openings 140a, 140b, respectively, for combining solder balls 15a, 15b, wherein a chip (not shown) is disposed by the upside solder ball 15b. In other words, the aforementioned fabrication process gradually forms layers from the downside of the packaging substrate 1 (i.e., contacting with the surface of the carrier board) to the metal bump 13b and the solder resist layer 14b that are used for disposing a chip. That is to fabricate a packaging substrate from implanting solder balls to disposing a chip.
Among them, one curing process must be performed once whenever forming one dielectric layer. Consequently, the structure of the original semi-cured dielectric material can be cured. Further, the more the number of curing undergone by one dielectric layer is, the more complete the gathering and shrinking of molecules in the dielectric layer become. All of the dielectric layers in the entire structure will be affected by the curing process each time. Therefore, the first dielectric layer 120a is cured four times, and the second, the third, and the fourth dielectric layers 120b, 120c, 120d are respectively curing three times, twice, and once.
In accordance with the above mentioned, the residual capability to gather and shrink of each dielectric layer is different due to the different curing number undergone by the first to the fourth dielectric layers 120a, 120b, 120c, 120d. Since the first dielectric layer 120a is curied most times, it hardly has any residual capability. That is, the residual capability of the second, the third, the fourth dielectric layers 120b, 120c, 120d is gradually increased in turn. In addition, since the residual capability of each dielectric layer of the packaging substrate will produce a stress pulling to the center from surroundings, the conventional packaging substrate 1 presents a warpage phenomenon showing a concave side from the fourth dielectric layer 120d and a convex side from the first dielectric layer 120a. That is, the chip-disposing side of the entire packaging substrate 1 presents a “smile”-like shape, which is a common feature in that kind of process. However, the substrate warpage phenomenon causes the fabrication of the packaging substrate and the subsequent package fabrication problems, thereby affecting the yield.
However, the solder resist layers 14a, 14b are respectively formed on the first dielectric layer 120a and the fourth dielectric layer 120d. Moreover, the opening 140a in the lower side of the solder resist layer 14a is greater than the opening 140b in the upper side of the solder resist layer 14b, and hence the actual coverage area of the lower side by the solder resist layer 14a is smaller than that of the upper side by the solder resist layer 14b. Consequently, the upper side of the solder resist layer 14b has more materials than the lower side of the solder resist layer 14a. The solder resist layer 14a, 14b both have molecule residual capability to gather and shrink. Therefore, the stress of the upper side of the solder resist layer 14b on the packaging substrate is greater than that of the lower side of the solder resist layer 14a. This will cause more serious degree of warpage of the packaging substrate 1.
According to the prior art, the solder resist layer and the outer circuit layer are not coplanar, and thus affecting the overall packaging yield and density.
Therefore, how to overcome warpage problems in the prior art is becoming one of the critical issues in the art.